Decade counter employing logic circuits

ABSTRACT

In a decade counter comprised of five threshold gates, each producing two output signals, the first signal indicative of a bit and the second of its complement. A clock pulse and its own first signal are applied to each circuit. The second signal produced by each circuit is applied to the remaining four circuits.

United States Patent I 3,600,561

[72] Inventor Robert Owen Winder [56] References Cited Prin on, NJ- UNITED STATES PATENTS [211 P 861,038 3,403,267 9/1968 Winder 307/289 [221 Wed sew-25,1969 3,434,058 3/1969 Winder.... 328/43 [45] Famed 1971, 3,456,126 7/1969 Kaplan 307/211 [731 Assgnee RCA 3,458,734 7/1969 Kaplan 328/37 x 3,460,098 8/1969 DeBlauw 328/42 X 3,508,033 4/1970 Turecki... 235/92 3,519,941 7/1970 Winder 307/221 X Primary Examiner-Maynard R. Wilbur [54] DECADE COUNTER EMPLOYING LOGIC Assistant Examiner-Joseph M. Thesz, J1.

CIRCUITS Att0meyH. Christoffersen 6 Claims, 6 Drawing Figs.

[52] US. Cl 235/92 LG, ABSTRACT: In a decade counter comprised of five threshold 235/92 R,328/45, 307/226, 235/92 MC gates, each producing two output signals, the first signal in- [51] 1nt.Cl ..H03k 21/00 dicative of a bit and the second of its complement. A clock [50] Field of Search 235/92, 60, pulse and its own first signal are applied to each circuit The 69,63,96,58;307/226, 220, 221,289; 328/45, second signal produced by each circuit is applied to the 37, 48, 41-43 remaining four circuits PATENTEDAUMIQIJ 8,600,561 sum 2 or 2 is 23 W Jib/way I DECADE COUNT R EMPLOYING LOGIC CIRCUITS j BACKGROUND or THE INVENTION This invention was conceived in the course of a government contract for the Department of Air Force.

Decade counters are widely used in many digital applications. The object of this invention is to provide such a counter which is relatively simple and fast. I

SUMMARY or THE INvENTIoN Five logic circuits each producing a first signal indicative of a bit and a second signal indicative of the complement of said bit. The first signal produced by each circuit is fed back to the same circuit and there is also fed back to each circuit the second signal produced by the remaining four circuits. A timing signal also is applied to each circuit.

' BRIEF DESCRIPTION OF THE. DRAWING DETAILED DESCRIPTION The counters of the present application are switched from state to state by an input timing signal I which varies in amplitude between a level representing binary 1 and a level representing binary 0. The counters each have 5 stages producing outputs a, b, c, d and-e, respectively, such that as t of decade counter goes through cycles (during each cycle t changes in value from O to I), the outputs a, b,c, d, 2 go through 1 cycle. (As will be shown shortly, 1 cycle consists of different counter 'states.)

- FIG. 1 shows the convention employed in the counter of FIG. 2. Each stageof'thecountercomprises athresholdgate 9 having five inputs, each with'weight l, and 'having a threshold of 4. Each stagealso includes 3 'OR gates 10, 11 and 12 connected to 3 of :the input terminals respectively of the threshold gate 9. j

The decade counter of FIG.-2 comprises'five stages 14-I8 such as shown in FIG. :1. Each stage has a feedbackuconnection 'fromthe firstoutput terminal thereofto one of its input terminals and'toan inputterminal mom of the OR gates of the stage. Thus,-in stage 14, the signal ais fed back to the input terminal '19 of thethresholdrgate and to one'input terminal of an OR gate. The second signal, that is, the complement signal, producedby'each stage is applied to the remaining four stages. Thus, signal 21 isapplied to twoOR-gates-of stage '15 and to one OR gatein each of stages 16, 17 and 18. The-timing signal t is applied directly-to the threshold gate of-each stage.

Th'eoperation of .the decadecounter of FIG. 2 is defined by the five Boolean equations which follow.

In th'e equations above, S" is the signum function. It has the value 1 when Nor more of its arguments have the value I, and otherwise has value 0, where N is the numeral within the brackets preceded by the minus sign. Inthe present instance,

r a b c d e O 0 0 0 l I 1.0 0 I l l 0 0 0 l 01 10 1101 0 0 l l 0 0 ll 1 l O 0- 01010 0 l l 0 l 01 0 l 0 0 01 l l 0 Ol l 010 010 l 101 l 0 O 0 0 l I 0 l0 1 l l 0 0 0 l O l 0 l l I 010 01 l 0 0 0 I1 I 0 0-1 0 010 01 10101 I 0 0 0 0 0 Il It may be observed from the Truth Table above that for each transition of t, that is, for each change in value from 0 to l or 1 to 0 of 2, only one of the quantities a through e changes value. An important advantage of operating in this way is that the counter is very fast-only one stage has to change its state in response to each change of the value of t.

A particularly attractive way of implementing the circuitsof FIGS. 1 and 2 is a modified'form of the threshold logic gate described by the present inventor in Threshold Logic Will Cut Costs Especially with Use of LSI," Electronics, May 27, 1968, pages 94 -103. The circuit shown on page 102, for example, may be modified in the manner shown in part in FIG. 3 to provide OR gate inputs. In the circuit shown on page 102 of the article, when a signal A represents a 1, current is steered through the transistor, corresponding to 32 of FIG. 3 into one path and when it represents a 0, currentis steered through the other transistor, corresponding to transistor 30 of FIG. 3, to the other path.

The modification required to implement a two-input OR function at an input to the threshold gate is shown in FIG. 3 of the present application. Each transistor such as 32 has in shunt with its-emitter-to-collector path the emitter-to-collector path of a second similar transistor 34. Now, if either A (which in the present instance may bean input such as a) or A (which inthe presentinstance may be an input such as E) represents a 1, one of the transistors 32 or 34 will conduct and a current representing '1 will flow in the collector circuit of either transistor 32 or 34.

'FIG. 3 shows only one of the OR input circuits which is necessary in one stage of the present counter. A complete stage includes three sets of transistors such as 32, 34 and 30 providing three two-input OR circuits for the stage. Thus,

rather than inputs A, B, vC of the article there are inputs (Ad-A -B and (C +C and in addition, each stage has twoadditional inputs corresponding to D and E of the circuit of the article. In addition, thethreshold of the circuit of the article is set to a value of 4 in'the use contemplated of the circuit in thepresent FIG. 2. The remaining sets of input transistors of the circuit of the article (receiving the inputs F...N) either are eliminated or the inputs'F...N are all made to carry a constant bias representing binary 0.

The circuitof the article modified in the way shown in part in FIG. 3 is attractive for implementing the present invention as itreadily may be integrated. Moreover, the circuit includes m'eans for obtaining a normal output from the signal present at one output lead and acomplemented output from the signal complemented output of each stage is applied to the remaining four stages. Each counter stage 41-45 is identical and may consist of the logic shown in FIG. 5 or of the logic shown in FIG. 6. The stage of FIG. 5 comprises five OR gates feeding an AND/NAND gate. Three of the OR gates have three input terminals and two of the OR gates have two input terminals. The circuit of FIG. 6 consists of five NOR gates feeding an OR/NOR gate. As in the circuit of FIG. 5, three of the input gates have three input terminals and two of the input gates have two input terminals.

The operation of the circuit of FIG. 4 is fully described in the five Bool ean equations which follow.

While the Truth Table for the operation of the circuit of FIG. 4 is not given, it is similar to the Truth Table above in that in response to each transition of I only one stage of the decade counter changes its value. Accordingly, the circuit of FIG. 4 is also capable of operating at high speed.

What I claim is:

l. A decade counter comprising, in combination:

five logic circuits, each producing a first signal indicative of a bit and a second signal indicative of the complement of said bit;

means for feeding back to each circuit the first signal produced by said circuit at the time said signal is produced;

means for feeding back to each circuit the second signal produced by each of the four remaining circuits at the time said four remaining'circuits produce said second signals; and

means for applying to each circuit a timing signal which changes in value between levels representing binary 1 and binary 0.

2. A decade counter as set forth in claim circuit comprises threshold gate means. I

3. A decade counter as set forth'in claim 1, wherein each circuit comprises five OR gates for receiving signals supplied to said circuit and an AND/NAND gate for receiving the five signals produced by the five OR gates and for producing said first and second signals.

4. A decade counter as set forth in claim 1, wherein each circuit comprises five NOR gates for receiving signals supplied to said circuit and an OR/NOR gate for receiving the five signals produced by the five NOR gates and for producing said first and second signals.

5. A decade counter as set forth in claim 1, wherein each circuit comprises a five-input circuit threshold gate, each input circuit of weight 1, and said gate having a threshold of four, three of said input circuits comprising OR gate means.

6. A decade counter as set forth in claim 1, wherein each circuit comprises a five-input threshold gate, each input of weight 1, and said gate having a threshold of four, and three two-input OR gates supplying signals to three of said inputs to said threshold gate, and further including a feedback connection for feeding back the first signal produced by said threshold gate to the fourth input thereto and to one input to one OR gate, said timing signal being applied to the fifth input to said threshold gate, and the other input to said one OR gate and the two remaining OR gates for receiving the second signal produced by the four other circuits of said counter.

1, wherein each Patent No.

Inventor(s) Robert 0 Winder Dated August 17, 1971 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

(table) read --llast "0" under col.

d should last "1" should be deleted c +E+b) (d-f)" should read "('B+'d+a) (c+'d)" should "(55% (b+ 6)" should read read

read

read

Signed and sealed this 25th day of January 1972.

ORM 90-1050 (10-69) min-eating Officer ROBERT GOTTSCHALK Conunissioner of Patents USCOMM-DC 50376-F6Q U 5 GOVERNMENT PRINTING OFFICE I969 O3GG-334 

1. A decade counter comprising, in combination: five logic circuits, each producing a first signal indicative of a bit and a second signal indicative of the complement of said bit; means for feeding back to each circuit the first signal produced by said circuit at the time said signal is produced; means for feeding back to each circuit the second signal produced by each of the four remaining circuits at the time said four remaining circuits produce said second signals; and means for applying to each circuit a timing signal which changes in value between levels representing binary 1 and binary
 0. 2. A decade counter as set forth in claim 1, wherein each circuit comprises threshold gate means.
 3. A decade counter as set forth in claim 1, wherein each circuit comprises five OR gates for receiving signals supplied to said circuit and an AND/NAND gate for receiving the five signals produced by the five OR gates and for producing said first and second signals.
 4. A decade counter as set forth in claim 1, wherein each circuit comprises five NOR gates for receiving signals supplied to said circuit and an OR/NOR gate for receiving the five signals produced by the five NOR gates and for producing said first and second signals.
 5. A decade counter as set forth in claim 1, wherein each circuit comprises a five-input circuit threshold gate, each input circuit of weight 1, and said gate having a threshold of four, three of said input circuits comprising OR gate means.
 6. A decade counter as set forth in claim 1, wherein each circuit comprises a five-input threshold gate, each input of weight 1, and said gate having a threshold of four, and three two-input OR gates supplying signals to three of said inputs to said threshold gate, and further including a feedback connection for feeding back the first signal produced by said threshold gate to the fourth input thereto and to one input to one OR gate, said timing signal being applied to the fifth input to said threshold gate, and the other input to said one OR gate and the two remaining OR gates for receiving the second signal produced by the four other circuits of said counter. 